Provides tools for analyzing aspects of PyRTL designs


Contains functions to estimate aspects of blocks (like area and delay) by either using internal models or by making calls out to external tool chains.

pyrtl.analysis.estimate.area_estimation(tech_in_nm=130, block=None)

Estimates the total area of the block.

Parameters:tech_in_nm – the size of the circuit technology to be estimated (for example, 65 is 65nm and 250 is 0.25um)
Returns:tuple of estimated areas (logic, mem) in terms of mm^2

The estimations are based off of 130nm stdcell designs for the logic, and custom memory blocks from the literature. The results are not fully validated and we do not recommend that this function be used in carrying out science for publication.

class pyrtl.analysis.estimate.TimingAnalysis(block=None, gate_delay_funcs=None)

Bases: :class:`object`

Timing analysis estimates the timing delays in the block

TimingAnalysis has an timing_map object that maps wires to the ‘time’ after a clock edge at which the signal in the wire settles

__init__(block=None, gate_delay_funcs=None)

Calculates timing delays in the block.

  • block – pyrtl block to analyze
  • gate_delay_funcs – a map with keys corresponding to the gate op and a function returning the delay as the value. It takes the gate as an argument. If the delay is negative (-1), the gate will be treated as the end of the block

Calculates the timing analysis while allowing for different timing delays of different gates of each type. Supports all valid presynthesis blocks. Currently doesn’t support memory post synthesis.

max_freq(tech_in_nm=130, ffoverhead=None)

Estimates the max frequency of a block in MHz.

  • tech_in_nm – the size of the circuit technology to be estimated (for example, 65 is 65nm and 250 is 0.25um)
  • ffoverhead – setup and ff propagation delay in picoseconds

a number representing an estimate of the max frequency in Mhz

If a timing_map has already been generated by timing_analysis, it will be used to generate the estimate (and gate_delay_funcs will be ignored). Regardless, all params are optional and have reasonable default values. Estimation is based on Dennard Scaling assumption and does not include wiring effect – as a result the estimates may be optimistic (especially below 65nm).


Returns the max timing delay of the circuit


Prints the max timing delay of the circuit

critical_path(print_cp=True, cp_limit=100)

Takes a timing map and returns the critical paths of the system.

Parameters:print_cp – Whether to print the critical path to the terminal after calculation
Returns:a list containing tuples with the ‘first’ wire as the first value and the critical paths (which themselves are lists of nets) as the second
static print_critical_paths(critical_paths)

Prints the results of the critical path length analysis. Done by default by the timing_critical_path() function.

pyrtl.analysis.estimate.yosys_area_delay(library, abc_cmd=None, block=None)

Synthesize with Yosys and return estimate of area and delay.

  • library – stdcell library file to target in liberty format
  • abc_cmd – string of commands for yosys to pass to abc for synthesis
  • block – pyrtl block to analyze

a tuple of numbers: area, delay

The area and delay are returned in units as defined by the stdcell library. In the standard vsc 130nm library, the area is in a number of “tracks”, each of which is about 1.74 square um (see area estimation for more details) and the delay is in ps.

May raise PyrtlError if yosys is not configured correctly, and PyrtlInternalError if the call to yosys was not able successfully

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